Data selecting and synchronizing circuit comprising plural gates and flipflops interconnecting data handling systems



Nov. 12, 1963 DATA SELECTING AND SYNCHRONIZING CIR GATES AND FLIP-FLOPS INTERCONNECTING DATA Filed Aug. 26, 1959 3 Sheets-Sheet 1 godin. .E

MP4@ m0 Y D. R. MAURE ETAL 3,110,866 DATA SELECTING AND SYNCHRONIZING CIRCUIT COMPRISING PLURAL GATES AND FLIP-FLOPS INTERCONNECTING DATA HANDLING SYSTEMS Nov. l2, 1963 3 Sheets-Sheet 2 Filed Aug. 26, 1959 Nov. 12, 1963 D. R. MAURE ETAT. 3,110,866

DATA sEDEcTING AND sYNcHRoNIzING CIRCUIT coMPRIsING PLURAL GATES AND FLIP-Hops INTERcoNNEcTING DATA HANDLING sYsTEMs Filed Aug. 26,l 1959 3 Sheets-Sheet 3 u! EQ g I 'al 25 EL: l im m z' I. INVENToRs g gg E9; 00a/GLAS R. MAI/RE s 23 3 ggz; g l BY BEM/AMW M. Maz/ss O y I I g g .lm m o i... /7 9 United States Patent O This invention relates generally to data processing systems and in particular to a circuit for selecting and synchronizing a unique signal from serial information containing a series of signals.

As information theory techniques improve, the necessity ot devising ways and means of conveying data from one information handling system to another in such manner as to be properly correlated and interpreted for useful purposes has become of paramount importance in the data processing iield. Accordingly, tms invention is concerned with the separation of desired intelligence signals or bits of certain types such as binary numbers or words from a group of similar intelligence or other signals or both, as the `case may be and, at the same time, impart synchronization of said desired intelligence signals between ldata transmitting computer equipment and data receiving, resolving or recording computer equipment during certain igiven operational conditions.. ln the instant invention, a number of predetermined signals are employed as known input signals which act as operators for actuating the various and sundry elements which are concomitantly receiving, selecting, sort-V ing, handling, coordinating, yand synchronizing the aforesaid desired information signals from the composite input serial information received from said 'data transmitter. Such input signals could, for example, be obtained from Sonar and associated `data group systems and be of the nature of range, bearing, or timing intelligence or the like, and when they are properly manipulated by the `components of the subject circuit, the accurate and synchronized transmission of information from one ship to another or one place to another is facilitated. Hence,

it can readily be seen that i1" the ldata is required on each ship, one acts as a transmitter and the other a receiver. For the purpose of avoiding errors due to such disturbances as noise, phase shift, and amplitude variation or in order to allow transmission of a plurality ot' groups of data over a single channel, the transmitter information is encoded. The receiver then decodes after Another object of this invention is to select signals ICC ciples for selection of one unique pulse from a series of signals.

Another object of this invention is to transmit a maximum amount of information over a given band width and still permit selection of unique data signals from a code with a minimum use of available time.

Another object is to provide a coded data selection and synchronization circuit which is substantially independent of the rate at which the data is received thereby.

yOther objects and advantages of the invention will hereinafter become more fully apparent from the iollowin description of the annexed drawings wherein:

FIG. l is a schematic diagram of an embodiment of the synchronizer and data selector constructed in accordance with the invention;

PEG. Z is a schematic diagram of a refined waveshape embodiment of the synchronizer and data selector constructed in accordance with the invention; and

FL'G. 3 is a graphical `representation of exemplary waveforms which may 'be employed as input signals to the subject invention along with typical representations 0f the output waveforms that may occur `as a result of using said input waveforms.

lReferring now to FlGS. l and 2 of the drawings, a plu- -rality of various and sundry input signals or pulses are fed finto the system circuit constituting this invention. These pulses may be obtained Vfrom any appropriate cornputing equipment capable of producing same in a manner such that they represent pertinent usable factors or parameters. For example, Sonar and associated computing equipment would be capable of producing these signals, but it is to be understood that use of the subject invention is not intended tok be limited to being used `in conjunction with Sona-r equipment alone, inasmuch as many other types oi data handling and processing apparatus would also be appropriate and could be used therewith to an advantage.

`One o such signals is a data receiver not-clock pulse and is applied to an input binding post `l2 or other electrical connector of conventional type. The not-clock pulse may be defined as a square vwaveform or timing trigger pulse which may be either symmetrical or unsymmetrical as necessary to perform a predetermined timing function for the purpose of controlling the time ofl an interrogation sequence. Another of such signals is a data receiver clock pulse whose waveform is similar to the `above mentioned not-clock pulse but is out of phase therewith. It, likewise, is used for the purpose of controlling a predetermined timing function such as the time of an interrogation sequence. Each of the foregoing signals is supplied by the aforementioned data receiver or associated apparatus which does not constitute a part of this invention but, nevertheless, they must be provided as input signals in order to effectively actuate the circuit of the subject invention.

In addition, another known but perhaps variable signal is supplied as a collateral signal to this circuit. lt is obtained from the data processing system constituting the data receiver and represents a master` timing parameter which is to be synchronizedwith similar Vparameters of the data processing system constituting the data transmitter. For instance, such signal may be a basic timing signal of such nature as to actuate a ring generator for providing a plurality of rings or pulses which, in turn, represent factors necessary for proper and timely data processing for synchronization purposes.

The signals containing the unique intelligence or data signals or bits such as binary words or numbers combined with a sequentially associated sync pulse are herein called the information-in signals. From these signals, said unique intelligence or data signal is selected and appropriately arranged with respect to said collateral signals and 8 said sync signal to facilitate their further use in the data receiver and associated equipment adapted to be responsive thereto in order to perform any given function of analog or digital nature or otherwise.

The aforesaid data receiver master cycle set pulse, the data receiver clock pulse and the information signals are fed into the circuit of this invention through conventional electrical connectors such as binding posts 13, ltd, and l5, respectively.

The information-in containing the data signals to be selected and synchronized is simultaneously applied to a first AND gate liti and a normally closed second AND gate i7. ri"nese AND gates are merely gating circuits with two or more inputs. They are conventional and often referred to as coincidence circuits because an output occurs only when all input signals coincide. The outputs from AND gates ld and i7 are applied to an GR gate i3. OR gates are, likewise, conventional and receive signals at two or more inputs and, when appropriately selected, they will pass signals presented at either input. Essentially, they are mixers with the exception that the output amplitude is not doubled should the two separate input pulses coincide, and, in addition, they provide isolation between the circuits feeding them.

The output of OR gate i3 is connected to a sync pulse out terminal l?, and during normal operating conditions it contains the sync pulse which is coupled to the clock or other timing means in the data receiver to provide a Zero time reference datum such as the aforesaid data receiver master cycle set pulse. The output of OR gate 18 is also coupled to a flip-lop 2li which may be of the binary counter type where the input signals are common to both grids and the output is taken from only one of the plates thereof. Said output is connected to the portion of a linear iiip-flop 2l which has been preset to be conductive during an initial, starting, or quasi-starting condition by the aforesaid master cycle set pulse from the data receiver. Since flip-ilop 2l has two separate input grids, an input to one of the grids, such as, for example, the grid of the aforementioned conductive portion, will cause it to assume one of its two stable states and repeated input pulses to this same grid will have no further effect, although a pulse on the other input grid will cause the ilipilop to change over to the other stable condition of operation. The output of AND gate 17 is coupled to that portion of flip-flop 2l which is initially set to be nonconductive for timely changing same to said other stable condition. In addition, the initially set non-conductive portion of Hip-flop 2li has its output fed back as an input to AND gate .i7 for the purpose of blocking a signal from going therethrough in event dip-lop 2l is in the wrong stable condition. Flip-hop 2l also has its initially set conductive portion connected to receive the data receiver master cycle set pulse in through a pair of circuit isolation diodes 22 and 23 with diode 22 connected to flip-flop as well. lf, in some instances, it becomes desirable to coordinate said master cycle set pulse with some other parameter from other or associated equipment, this may be accomplished by using an auxiliary AND gate which is responsive to said set pulse and said parameter signal as an intermediate input stage to the aforementioned diodes and flip-flops. Likewise, it is within the purview of this invention to include a master cycle set pulse excited ring generator either separately or in conjunction with said auxiliary AND gate as an impetusfor ilip-tlop 2l, although such components are not employed in the subject preferred embodiment.

As well as being applied to ANDV gates i6 and 11.7, the information-in signals are simultaneously applied to a ilip-flop 24 at its momentary original conducting portion along with the aforementioned not-clock pulse from the data receiver which is also applied thereto at the original non-,conducting portion. rhe output from flip-flop 24 is coupled to an AND gate 25 along with the aforesaid clock. pulse from the data receiver for timely actuating said AND gate 2S to effect proper sequential arrangement of the information-out, including the selected intelligence and data signals or bits with respect thereto, and to effect appropriate arrangement with respect to the sync output signal as well as at an output terminal 23.

Briefly, the operation of the circuit system constituting this invention is as follows. lt has been found, for example, that a waveform using a single sinewave cycle to represent one bit or pulse of intelligence works well as the information-in signal. Thus, if there is a bit in every slot, the waveform is almost a continuous sinewave. And if a minimum number of bits exist, there may only be three single sinewave cycles in a maior cycle, although it will be readily recognized that there are a large number of possible combinations available. This sinewave is gated into the subject system after a half cycle of the information rate has elapsed which, in turn, produces an out-of-phase sinewave that is the unique pulse detected in the synchronization circuit.

Tl e invention system opera-tes on the premise that the information-in consists of at least two data pulses and only one sync pulse in any major cycle with the sync pulse displaced in time or out of phase with the data pulses. When operating normally, the information-in is in the form of narrow pulses which coincide in time with the center of the data receiver not-clock pulse, and the data receiver processing system is synchronized with the received data. Flip-flop 24E- converts the narrow information pulses into wide pulses by turning itself on with each bit of information and turning itself oli with the not-clock pulses. Flip-liep 24 and the `clock pulses open AND gate 25 and produce ya standard width pulse for each bit of information. ln event there is no input data and the data receiver clock is free-running, sync flip-flops Ztl and 2l will be in reset position with the output portio-n of )flip-flop 2l in a non-conductive state. But, in event that information signals are being received and that they `are in phase with the clock pulse, then the sync pulse will be in phase with the not-clock pulse and only information pulses will be allowed to enter through AND gate 16, since AND gate 17 is normally ot and is controlled by the state of ilip-op 21 and the feedback therefrom.

The rst bit of information which enters through AND gate i6 will reset the data receiver clock so that the sync ilip-llops will not be reset until the predetermined master cycle set pulse -has been received thereby through the isolation diodes. lf the first bit of information is not exactly in the center of the clock pulse, the rst reset of the clock will synchronize the succeeding information pulses with the `center of the clock pulse, and, likewise, the sync pulse will `coincide with the center of the not-clock pulse.

The second bit of information enters through AND gate 16 and again resets the clock in the same manner as before so that the sync flip-flops will not be set for n pulses after reset. The second bit of information changes lthe `state of hip-flop Ztl which, in turn, changes the state of flip-flop 2l and opens AND gate 17. Now both AND gates lo and i7 are open, 'allowing information to still reset lthe clock and change the state of hip-flop 20 but will not change the state ,of flip-flop 21. Because AND gate 17 is open, the rsync pulse enters, resets the data receiver clock, changes the state of flip-liep Ztl, and resets lip-I'lop Ztl. When both the receiver clock and flip-flop 2l are reset, {lip-dop 2l closes AND gate 17. Then the sync pulse is in phase with lthe clock pulse Iand the bits are in phase with not-clock pulse and, therefore, information bits can no longer reset the `data lreceiver clock. Before the next sync pulse arrives some pre-determined number of pulses away, the sync flip-flops `are reset, and `thereafter only flip-flop Ztl will change its state during normal operation. Thus, it can be seen that the selected unique signals or bits constituting the information-out are properly associated with the sync output signal from a time-phase aspect and sent' to the data receiver equip- `ment in such a synchronized arrangement.

Referring now to FIG. 2, it will be noted that the circuit embodiment depicted therein is basically similar to the embodiment of FIG. l with the exception that a few optimizing components enabling the modification :and refinement of the various and sundry intermediate signal waveshapes have been included .to produce improved operation of their respective individually actuated system elements by characterizing said waveshapes in such manner as to better conform with the natural inherent requirements thereof for m-ore efficient operation. The elements which are common to the embodiments of both figures have :been given the same reference numbers for `the purpose of simplicity of description. Hence, the explanation of .the basic major elements `of the ysubject embodiment is comparable to that presented to explain the structural `elements of the device Iof FiG. 1 and their interconnection, -and should -be referred to for each purpose.

One of th-e .added features of the embodiment f FIG. 2-

consists of inclu-ding a series connected integrator 29 and cathode follower Sti :between notclock pulse input terminal and `an input to AND gate 17. Since high frequency harmonic components of waveforms are diminished through integrator networks, said integrator 29 effects filter refinement of said not-clock pulse as it travels therethrough enroute to said AND gate 17. Cathode follower Sf is lused in conjunction therewith for circuit isolation purposes.

Another of the added features of the subject embodiment include incorporation of a pulse amplifier 3f to increase the strength of the output of OR gate 18 and a cathode follower 32 to isolate gates 16, i7, and i3 and pulse amplifier 31 from sync flip-flops 29 and 2.1.

A pulse amplifier 33 is used between the master cycie 'set pulse in fand isolation diodes 2liand 25 `for increased sensitivity purposes. Included in the feedback circuit between the output of flip-flop 2i and input yof AND gate 17 are series connected integrator 34 and cathode follower 35 which .are used as a signal filter and a circuit isolator, respectively.

The operation of the embodiment 4of FIG. 2 is substantially comparable to that of the embodiment of FIG. l with the possible exception that the former may be somewhat more efiicient than the latter due to the intermediate signal refinement just mentioned.

The new method and means of signal transmission constituting this invention as it is disclosed in either of the above preferred embodiments may, for example, use opposite phases of a sine ywave to distinguish between a one and a zero When transferring from a one to a zero or from a zero to a one, a space is made equal to half the time of a single sine wave. rIhis space, of course, is necessary to prevent a discontinu-ity and unbalance of thewaveform, and it occurs only during the clock time, which, in turn, leaves a space during not-clock time as a unique condition for the synchronizing pulse.

FIG. 3 shows the waveforms of the various data configurations. while FIG. .3(b) shows the not-clock pulses. FIG. 3(0) illustrates the converted data in a form ywhich is available for being transmitted by a radio link or any other suitable data processing system. It should be noted that a space occurs during the clock pulse time only, when there is a change from a one to a zero or vice versa.

Recovering the data after transmession is very simple by looking atV the data waveforms only duringA the notclock time. Notice, for instance, in FIG. 3(c) that'there EG. 3(a) discloses exemplary clock pulses prior art because a one pulse is the peak negative state and -a Zero pulse is the pevalt positive state.

As stated previously, the master pulse occurs as a space during the not-clock time and this is a unique condition since there are no other spaces during the not-clock time. FlG. 3(c) sholws the sync pulse during the last two clock times. Two clock times are used for thesync pulse, of course, in order to keep the total space time equal to one clock and not-clock period.

it can, therefore, be readily seen that if exemplary signals having the respective waveforms of FiG. 3 are applied to the subject invention the waveform shown as FiG. 3(d) may result tas the output signal therefrom which is ready to be transmitted to any other remote second data processing system for further use thereby. As can be seen from said output signal, the input signals have been respectively phase related, arranged, and properly correlated by the device constituting this invention to effect the desired exemplary output signal emanating therefrom as shown in the FiG. 3(51') representation.

Obviously, many other modifications and variations of the present invention are possible in the light of the above teachings. It is therefore, to be understood that within the scope of the appended claims the invention may be practiced otherwise thanas specifically described.

What is claimed is:

l. A data selecting and synchronizing circuit comprising in combination, a first AND gate having ya trio of inputs and an output, a second AND gate having a pair of inputs and an output, a third AND gate having la pair of inputs and an output, an OR gate having a pair of inputs and an output, a first iiipdiop having la pair of inputs and an output, a second flip-hop having an input and an output, a third flip-flop having a trio of inputs and an output, said rst and second AND gates and said first flipflop having one of their inputs interconnected to receive an information signal, said first ANDy gate and said first fiip-lop having another of their inputs interconnectedV timing pulse, the other input of said third AND gate being coupled to the output of said first fiip-flop, said pair of OR gate inputs respectively connected to the outputs of saidfirst and second AND gates, and said OR gate output connected to the input of said second Afiip-flop to provide a ,sync pulse signal output, one of the inputs of said third liip-iop connected to the output of said second flip-flop, another of the inputs of said third fiip-flop coupled to the output of said first AND' gate, a pair of diodes having the inputs thereof interconnected to recenve a master sync signal, the outputs of said diodes respectively connected to said one input and the remaining input of theaforesaid third flip-flop, the output of said third fiip-fiop connected to the remaining input of said first AND gate, and the output of said third AND gate providing a predetermined data signal output. 2. A data selecting and synchronizing circuit comprising in combination, a first AND gate having a trio of noise ratio is for most practical purposes considerably inputs and an'output, a second AND gate having a pair of inputs and an output, a third AND gate having a pair of inputs and an output, an OR gate having a pair of inputs and an output, a ,first dip-flop having a pair of inputs and an output, a second fiipffop having an input and an output, a-third fiipdiop having a trio of inputs and an output, said first and second AND gates and said first fiipflop having 'one of their Vinputs interconnected for receiving a predetermined information signal, a first integrator having an input and an output, a first cathode follower interconnecting the output of said first integrator and another of the inputs of the aforesaid first AND gate, the input of'said first integrator connected to said one input of, said first flip-flop for receiving a rst predetermined timing signal, said second AND gate and said third AND gate having one of their inputs interconnected for receiving a second predetermined timing pulse, the other input of said third AND gate being coupled to the output of said first -iiip-op, said pair of GR gate inuts respectively connected to the outputs oi said first and second AND gates, a pulse amplifier connected to the output of said Oil gate, a second cathode follower connected to the output of Said pulse amplifier, the output of said second cathode follower being connected to the input of said second iiip-ilop to provide a sync pulse signal output in addition, one of the inputs of said third tlip-op connected to the output of said second iip-ilop, another of the inputs of said third -ip-lop coupled to the output of said first AND gate, a pair of diodes having their inputs interconnected and their outputs respectively connected to said one input and the remaining input of the aforesaid third dip-dop, a puise amplitler for receiving a master sync signal having its output coupled to the interconnection of the inputs of said diode, a second integrator connected to the output of said third dip-flop, a third cathode follower interconnecting the output of said second integrator and the remaining input of said first AND gate, and the output of said third AND gate providing said predetermined data signal at the output thereof.

3. A synchronizer and data selector system comprising in combination, rst conductor means for receiving serial information containing a unique code signal and a sync pulse from a rst data processing system, a second and third conductor means for respectively receiving a pair of predetermined signals `from a second data processing system, means interconnecting said iirst, second, and third conductor means for respectively and relatively positioning said sync pulse and said predetermined signals within a unitary continuous signal including a first AND gate for receiving said sync pulse and one of the aforesaid pair of predetermined signals, a second AND gate for receiving said sync pulse, the other of said pair of predetermined signals, and a timing signal, an OR gate connected to the outputs of said first and second AND gates, a binary counter lip-op connected to receive the output of said Gl?. gate, and a linear flip-dop coupled to the output of said binary counter flip-hop and to said second AND gate for feeding said timing signal thereto, means connected to said positioning means for selectively phase relating said unique code signal with the aforesaid relatively positioned sync puise and a pair of predetermined signals Within said unitary continuous signal, and fourth conductor means responsive to said last mentioned phase relating means for supplying the output therefrom to said second data processing signal.

4. A synchronizer circuit for passing a unique code signal between two data processing systems comprising in combination, means for receiving serial information containing a unique code signal from one of said data processing systems, means for receiving a pair of predetermined timing signals from the other of said data processing systems, means connected to said serial information receiving means for selecting and separating said unique code signal from said serial information including a bistable multivibrator, said multivibrator having a first half responsive only to said pair of predetermined timing signals for sequentially changing the state thereof., said multivibrator having an output proportional to and representative of said unique code signal when said rst hait is in a conductive state, and gate means connected to said multivibrator responsive to both said unique code signal and the other of said pair of predetermined timing signals for passing said unique code signal when said unique code signal and the other of said pair of predetermined timing signals are simultaneously received thereby, means interconnecting said serial information receiving means and said selecting and separating means for positioning said unique code signal with said pair of predetermined timing signals in a predetermined relative phase relationship, and means coupled to said positioning means for conveying said phase related unique code signal to the aforesaid other data processing system.

No references cited. 

4. A SYNCHRONIZER CIRCUIT FOR PASSING A UNIQUE CODE SIGNAL BETWEEN TWO DATA PROCESSING SYSTEMS COMPRISING IN COMBINATION, MEANS FOR RECEIVING SERIAL INFORMATION CONTAINING A UNIQUE CODE SIGNAL FROM ONE OF SAID DATA PROCESSING SYSTEMS, MEANS FOR RECEIVING A PAIR OF PREDETERMINED TIMING SIGNALS FROM THE OTHER OF SAID DATA PROCESSING SYSTEMS, MEANS CONNECTED TO SAID SERIAL INFORMATION RECEIVING MEANS FOR SELECTING AND SEPARATING SAID UNIQUE CODE SIGNAL FROM SAID SERIAL INFORMATION INCLUDING A BISTABLE MULTIVIBRATOR, SAID MULTIVIBRATOR HAVING A FIRST HALF RESPONSIVE ONLY TO SAID PAIR OF PREDETERMINED TIMING SIGNALS FOR SEQUENTIALLY CHANGING THE STATE THEREOF, SAID MULTIVIBRATOR HAVING AN OUTPUT PROPORTIONAL TO AND REPRESENTATIVE OF SAID UNIQUE CODE SIGNAL WHEN SAID FIRST HALF IS IN A CONDUCTIVE STATE, AND GATE MEANS CONNECTED TO SAID MULTIVIBRATOR RESPONSIVE TO BOTH SAID UNIQUE CODE SIGNAL AND THE OTHER OF SAID PAIR OF PREDETERMINED TIMING SIGNALS FOR PASSING SAID UNIQUE CODE SIGNAL WHEN SAID UNIQUE CODE SIGNAL AND THE OTHER OF SAID PAIR OF PREDETERMINED TIMING SIGNALS ARE SIMULTANEOUSLY RECEIVED THEREBY, MEANS INTERCONNECTING SAID SERIAL INFORMATION RECEIVING MEANS AND SAID SELECTING AND SEPARATING MEANS FOR POSITIONING SAID UNIQUE CODE SIGNAL WITH SAID PAIR OF PREDETERMINED TIMING SIGNALS IN A PREDETERMINED RELATIVE PHASE RELATIONSHIP, AND MEANS COUPLED TO SAID POSITIONING MEANS FOR CONVEYING SAID PHASE RELATED UNIQUE CODE SIGNAL TO THE AFORESAID OTHER DATA PROCESSING SYSTEM. 